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Lecture 1
Course Introduction, Technology Trends, Performance Laws, and Rules of Thumb
slides: 2up.pdf, 6up.pdf | Lecture2
Benchmarks, Performance, and Cost, Instruction Set Architecture
HW #0 Due
slides: 2up.pdf, 6up.pdf |
Lecture3
Review of Control, Datapath, Pipelining
slides: 2up.pdf, 6up.pdf | Lecture4
Pipelining Complications---Data and Control Hazards, Case Study of MIPS R4000
slides: 2up.pdf, 6up.pdf |
Lecture5
Instruction Level Parallelism, Compiler perspective
slides: 2up.pdf, 6up.pdf | Lecture6
Case Studies: CDC 6600 Scoreboarding, Tomasulo's Algorithm
slides: 2up.pdf, 6up.pdf |
Lecture7
Branch Prediction, Sup.pdferscalar, VLIW, SW Pipelining, Trace Scheduling, Conditional Execution, Speculation, Limits
slides: 2up.pdf, 6up.pdf | Lecture8
Microarchitectures and Trends:
The Microarchitecture of Sup.pdferscalar processors (paper)
slides: 2up.pdf, 6up.pdf |
Lecture9
Complexity Effective Processors paper
IPC vs. Clockrate paper | Lecture10
Processor Design for Portable Systems paper
Energy Dissipation in General Purpose Proc paper
Dynamic Thermal Management paper |
Lecture11
Memory Hierarchy--4 Qs, 3Cs, reducing miss rate
slides: 2up.pdf, 6up.pdf | Lecture12
Memory Hierarchy--3Cs, reducing miss rate, improving hit time
slides: 2up.pdf, 6up.pdf |
Lecture13
Memory Hierarchy--program/compiler optimizations, reducing miss penalty
(CProf paper)
slides: 2up.pdf, 6up.pdf | Lecture14
Main Memory, Virtual Memory, Page Tables & TLBs, Managing the Memory Hierarchy
slides: 2up.pdf, 6up.pdf |
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