Great Ideas in Computer Architecture (Machine Structures)

Course Description:

The subjects covered in this course include C and assembly language programming, how higher level programs are translated into machine language, the general structure of computers, interrupts, caches, address translation, CPU design, and related topics.

Wk	Lecture Topic	Lab	Assignment Due
1	Introduction and C vs. Assembly-- Introduction (2 up), (6 up)
2	HW/SW Interface: C vs. Assembly-- Operands (2 up), (6 up)	Lab 1, Part 1: C Environment and Strings	HW#1: HW/SW interface  Solution
	HW/SW Interface: C vs. Assembly-- Characters (2 up), (6 up)
	HW/SW Interface: C vs. Assembly-- Functions (2 up), (6 up)
3	Holiday	Lab 1, Part 2: More C: Pointers and Number Representation	HW#2: rgrep Due Friday@23:59:59 rubric
	HW/SW Interface: C vs. Assembly-- Numbers (2 up), (6 up)
	HW/SW Interface: C vs. Assembly-- Instructions (2 up), (6 up)
4	Floating Point and Pointers Revisited (2 up), (6 up)	Lab 2, Part 1: Assembly Practice	Project#1: MIPS Instruction Set Emulator  Two Weeks, Due Saturday 9/18 (Part 1),  9/25 (Part 2)@23:59:59
	Technology Trends and Components of a Computer  (2 up), (6 up)
	Datacenters and Cloud Computing (2 up), (6 up)
5	Request and Data-Level Parallelism (2 up), (6 up)	Lab 2, Part 2: More Assembly Practice
	Compilation vs. Interpretation (2 up), (6 up)
	Quantitative Evaluation (2 up), (6 up)
6	Quantitative Evaluation (2 up), (6 up)	Lab 3, Part 1: Cache Blocking	HW#3: C/MIPS and Caches Solution
	Memory Hierarchy: Direct Mapped Caches (2 up), (6 up)
	Memory Hierarchy: Cache-Memory Interface (2 up), (6 up)
7	Memory Hierarchy: Cache Performance (2 up), (6 up)	Lab 3b: EC2
	Midterm (6-9 PM), Pimental 1
	Data Level Parallelism: Flynn Taxonomy (2 up), (6 up)
8	Data Level Parallelism: Intel SSE SIMD Instructions (2 up), (6 up)	Lab 4a: Data Parallelism	Project 2: Map-Reduce Parallelism  Two Weeks, Due Friday, 10/22@23:59:59
	Thread Level Parallelism
	Thread Level Parallelism
9	Thread Level Parallelism	Lab 4b: Thread Parallelism
	Transistors
	HW Abstraction Layers
10	HW Abstraction Layers	Lab 5: Logisim	HW 4: Digital Design and FSMs  Due Friday@23:59:59
	HW Abstraction Layers
	State and Metastability
11	Instruction Level Parallelism		Project 3: Processor Design  Two Weeks, Due Friday, 11/12@23:59:59
	Instruction Level Parallelism
	Instruction Level Parallelism
12	In More Depth: Caches	Lab 6: Performance Improvement
	In More Depth: Caches
	In More Depth: Protection
13	In More Depth: Protection
	In More Depth: Dependability		Project 4: Performance Code Two Weeks, Due Mon, 11/29@Programmming Contest
	In More Depth: Dependability
14	Spare
	Spare
	Thanksgivings Holiday
15	Programming Contest (evening)
	Programming Contest Results
	Course Retrospective